Interrupts :D
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@@ -20,6 +20,25 @@
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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#define CASCADE_IRQ 2
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#define IDT_MAX_DESCRIPTORS 32
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typedef struct {
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uint16_t isr_low; // The lower 16 bits of the ISR's address
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uint16_t kernel_cs; // The GDT segment selector that the CPU will load into CS before calling the ISR
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uint8_t reserved; // Set to zero
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uint8_t attributes; // Type and attributes; see the IDT page
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uint16_t isr_high; // The higher 16 bits of the ISR's address
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} __attribute__((packed)) idt_entry_t;
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typedef struct {
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uint16_t limit;
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uint32_t base;
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} __attribute__((packed)) idtr_t;
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typedef struct {
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uint32_t ds;
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uint32_t edi, esi, ebp, esp, ebx, edx, ecx, eax;
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uint32_t int_no, err_code;
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uint32_t eip, cs, eflags, useresp, ss;
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} INT_registers_t;
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inline void PIC_sendEOI(uint8_t irq) {
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if (irq >= 8) { // slave also needs EOI
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@@ -27,4 +46,17 @@ inline void PIC_sendEOI(uint8_t irq) {
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}
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outb(PIC1_COMMAND,PIC_EOI);
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}
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extern void PIC_remap(int offset1, int offset2);
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void PIC_remap(int offset1, int offset2);
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__attribute__((noreturn))
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void INT_exhand(INT_registers_t regs);
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void INT_IRQ(uint8_t IRQ, INT_registers_t regs);
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void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags);
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void idt_init();
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__attribute__((aligned(0x10)))
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extern idt_entry_t idt[256];
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extern idtr_t idtr;
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extern void* isr_stub_table[];
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extern void* irq_stub_table[];
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extern uint8_t INT_vectors[IDT_MAX_DESCRIPTORS];
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extern char *exception_messages[];
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