started work on interrupts

src/headers/interrupts.h

@@ -0,0 +1,30 @@
+#pragma once
+#include "stddef.h"
+#include "stdlib.h"
+// thank you osdev.
+#define PIC1		0x20 // master PIC
+#define PIC2		0xA0 // slave PIC
+#define PIC1_COMMAND	PIC1
+#define PIC1_DATA	(PIC1+1)
+#define PIC2_COMMAND	PIC2
+#define PIC2_DATA	(PIC2+1)
+#define PIC_EOI		0x20
+#define ICW1_ICW4	0x01		/* Indicates that ICW4 will be present */
+#define ICW1_SINGLE	0x02		/* Single (cascade) mode */
+#define ICW1_INTERVAL4	0x04		/* Call address interval 4 (8) */
+#define ICW1_LEVEL	0x08		/* Level triggered (edge) mode */
+#define ICW1_INIT	0x10		/* Initialization - required! */
+#define ICW4_8086	0x01		/* 8086/88 (MCS-80/85) mode */
+#define ICW4_AUTO	0x02		/* Auto (normal) EOI */
+#define ICW4_BUF_SLAVE	0x08		/* Buffered mode/slave */
+#define ICW4_BUF_MASTER	0x0C		/* Buffered mode/master */
+#define ICW4_SFNM	0x10		/* Special fully nested (not) */
+#define CASCADE_IRQ 2
+
+inline void PIC_sendEOI(uint8_t irq) {
+	if (irq >= 8) { // slave also needs EOI
+        outb(PIC2_COMMAND,PIC_EOI);
+    }
+	outb(PIC1_COMMAND,PIC_EOI);
+}
+extern void PIC_remap(int offset1, int offset2);

src/kernel/interrupts.c

@@ -0,0 +1,17 @@
+#include "../headers/interrupts.h"
+
+void PIC_remap(int offset1, int offset2) {
+    outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4);  // starts the initialization sequence (in cascade mode)
+	outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
+	outb(PIC1_DATA, offset1);                 // ICW2: Master PIC vector offset
+	outb(PIC2_DATA, offset2);                 // ICW2: Slave PIC vector offset
+	outb(PIC1_DATA, 1 << CASCADE_IRQ);        // ICW3: tell Master PIC that there is a slave PIC at IRQ2
+	outb(PIC2_DATA, 2);                       // ICW3: tell Slave PIC its cascade identity (0000 0010)
+	
+	outb(PIC1_DATA, ICW4_8086);               // ICW4: have the PICs use 8086 mode (and not 8080 mode)
+	outb(PIC2_DATA, ICW4_8086);
+
+	// Unmask both PICs.
+	outb(PIC1_DATA, 0);
+	outb(PIC2_DATA, 0);
+}